Circuit designers analyze the timing of circuit designs in order to verify that a circuit implemented from the circuit design will operate as intended. Setup and hold time violations are identified and paths of the circuit design adjusted accordingly. A critical path is generally recognized as any path that has a setup or hold time violation.
Static timing analysis (STA) uses timing models of circuit elements to determine delays of paths in the circuit design. The timing models associate delay values with circuit elements, and the delay of a path can be computed as the sum of the delay values of the circuit elements on the path. STA sometimes produces results that are too optimistic or overly pessimistic. If the path delay is too optimistic, the physical circuit path may violate timing constraints even though STA indicated the path is legal. If the delay is too pessimistic, the physical circuit path may have enough slack to have supported a faster clock speed without violating timing constraints.
STA tools generally assume that topologically similar clock paths have the same delay. A clock path begins at a clock source and terminates at the clock pin or clock-enable pin of a bi-stable circuit. That is, clock paths having the same length and same line widths would have the same delay. In order to handle process-related differences between the delays of topologically similar clock paths, STA tools have assumed a worst-case delay for the paths. However, assuming the worst-case delay may result in an implemented circuit that operates at frequency that is slower than a frequency that may be otherwise achieved.